To increase the storage density of semiconductor memories, the size of memory cells must be reduced. Smaller memory cells also lead to faster speeds and lower power consumption.
A widely-used semiconductor memory is the "floating gate" memory. A floating gate memory has a floating gate interposed between a channel and a control gate. Information is represented by storing a plurality of charges (e.g., hundreds of thousands) on the floating gate. The information stored in a floating gate memory can be determined because differing amounts of charge on the floating gate will shift the threshold voltage of the transistor. A relatively low threshold voltage (e.g., no excess charges on the floating gate) can be used to represent a stored logic `0`, and a relatively high threshold voltage (e.g., a plurality of charges on the floating gate) can be used to represent a stored logic `1.` For a detailed discussion of floating gate memories, the reader is referred to S. M. Sze, "Physics of Semiconductor Devices," John Wiley & Sons, pp. 496-497 (1981), which is incorporated into this application by reference in its entirety.
Recently, MOS memory cells have been fabricated which are capable of storing and detecting the presence or absence of a single charge to represent either a logic `1` or logic `0.` A device capable of this feat is referred to as a Single Electron MOS Memory (SEMM).
A previous SEMM design, disclosed in Kazuo Yano et al., "Room-Temperature Single-Electron Memory," IEEE Trans. Elec. Devices, Vol. 41, No. 9, pg. 1628 (September 1994), uses a tiny polysilicon strip which forms the source-to-drain path of the SEMM to store a discrete number of charges. An electron percolation path in the polysilicon strip forms the channel of the device, and one of the polysilicon grains next to the conduction path can act essentially in the same manner as a floating gate. However, because this structure relies on the polysilicon grain structure of the source-to-drain path as the storage medium, it inherently prevents a precise control of the channel size, the floating gate dimension, and the tunnel barrier.
In another previous SEMM design, disclosed in Sandip Tiwari, "A Silicon Nanocrystals Based Memory," App. Phys. Letters, Vol. 68, No. 10, pg. 1377 (March 1996), a conventional floating gate is replaced with a plurality of nanocrystal grains in a traditional floating gate memory. However, utilizing this approach, the size of the silicon nanocrystals forming the plurality of floating gates and the tunnel barriers associated with each floating gate will have an inherently broad distribution.
While both of these previous approaches strive to alleviate the challenges presented by nanofabrication (i.e., the fabrication of structures approaching the size of a nanometer), both rely on the use of statistically variant floating gate structures which lead to undesirable fluctuations in threshold voltage shifts and in the charging voltage, therefore making such structures unsuitable for large-scale integration. A commercially practical SEMM would require a voltage for charging a single electron to a floating gate to be discrete and well separated, and to result in a sufficient and predictable threshold voltage shift when a single electron is stored.